1. Technical Field
This invention generally relates to the field of semiconductor processing and integrated circuit manufacturing. More specifically, the present invention relates to improving the fabrication process for certain integrated circuit devices.
2. Background Art
Today, our society is heavily dependent on high-tech electronic devices for everyday activity. Integrated circuits are the components that give life to our electronic devices. Integrated circuits are found in widespread use throughout our country, in appliances, televisions and personal computers, and even in automobiles. Additionally, modern manufacturing and production facilities are becoming increasingly dependent on the use of machines controlled by integrated circuits for operational and production efficiencies. Indeed, in many ways, our everyday life could not function as it does without integrated circuits. These integrated circuits are manufactured in huge quantities in our country and abroad. Improved integrated circuit manufacturing processes have led to drastic price reductions and performance enhancements for these devices.
The traditional integrated circuit fabrication process is a series of steps by which a geometric pattern or set of geometric patterns is transformed into an operational integrated circuit. An integrated circuit consists of superimposed layers of conducting, insulating, and device-forming materials. By arranging predetermined geometric shapes in each of these layers, an integrated circuit that performs the desired function may be constructed. The overall fabrication process consists of the patterning of a particular sequence of successive layers. The patterning process used to fabricate integrated circuits is typically performed using lithography followed by a variety of subtractive (etch) and additive (deposition) processes.
Photolithography, a type of lithographic process, is used in the manufacturing of semiconductor devices, integrated optics, and photomasks. The process typically involves the following steps: applying a layer of a material (known as a photoresist, or resist) that will react when exposed to actinic or activating energy; exposing portions of the photoresist to actinic energy such as light or other ionizing radiation, i.e., ultraviolet, electron beams, X-rays, etc., thereby changing the solubility of portions of the resist; and developing the resist by washing it with a basic developer solution, such as tetramethylammonium hydroxide ("TMAH"), thereby removing the non-irradiated (in a negative resist) or irradiated (in a positive resist) portions of the layer.
As the need for higher and higher levels of integration has arisen in the industry, the need for a larger number of patterns, lines, and spaces in a given area has increased dramatically. In response, the scaling of lithographic features has been an essential aspect of enhancing the performance and density of semiconductor devices. Lithographic scaling has been achieved primarily by three methods: increasing the numerical aperture (NA) of the exposure tool; reducing the exposure wavelength of the actinic energy or ionizing radiation source; and improving the response of the photoresist. These three parameters are expressed in the Rayleigh model for lithographic resolution, as given by the equation: EQU R=k.lambda./NA
where R is the resolution, k is an empirically derived parameter that is dependent on photoresist performance, .lambda. is the exposure wavelength, and NA is the numerical aperture of the expose tool.
The "k" factor is reduced by resists that can provide a wider focus/expose process window for a high resolution feature. Historically, this "k" factor has been reduced by altering the resist components, for example: by adding resins and sensitizers with higher contrast; employing thinner resist films; and using antireflective films. The reduction of the "k" factor is becoming more important because NA values are reaching their limit at 65-70, and because development work at reducing the expose wavelength from the state-of-the art of 248 nm is still in preliminary stages. There are, however, practical limits to the current state of the art in photolithography.
Integrated circuits are chemically and physically integrated into a substrate material, such as a silicon or gallium arsenide wafer, by combining electrically conductive, semi-conductive, and dielectric (insulating) layers or regions. The layers and regions are arranged to form electronic components or devices such as transistors, diodes, and capacitors. Thousands of these devices are formed essentially simultaneously on the surface of a single wafer of semiconductor material during processing.
For example, in a typical fabrication process, a layer of aluminum or some other metal is deposited on the surface of the wafer substrate. The metal layer is patterned to form interconnect paths along the surface of the wafer substrate. The substrate typically contains certain dopant materials which form transistor components. Examples of possible substrate components include N-well or P-well sources, drains, and junctions. In most processes, an insulating or dielectric layer is then deposited over the first metal layer. Vias, or holes, are then created in the dielectric layer and a second metal layer is deposited over the dielectric layer. The second metal layer covers the intervening dielectric layer and fills the via openings in the dielectric layer down to the first metal layer. These filled via openings provide electrical connections between the first and second metal layers. The second metal layer is also patterned to form additional circuit devices and paths. The dielectric layer acts as an insulator between the first and second metal layer. This process can be repeated with additional layers as necessary to create the desired functionality in the circuits located on the wafer. Additional circuit components such as isolation regions, wells, and gates are discussed below.
Many circuits manufactured today incorporate shallow trench isolation (STI) areas as part of the fabrication process. STI regions are typically used to electrically isolate certain circuit components from other circuit components. An STI region is typically created by etching a trench in the surface of the wafer and filling it with oxide, followed by polishing the surface. The n-well region and the p-well region are complementary regions typically formed by selectively masking the surface of the silicon wafer, with an n-well mask and a p-well mask, ion implanting a dopant species, followed by an annealing process to activate the dopant species. The n-well is typically created used phosphorous ion dopant implants and the p-well is typically created using boron ion dopant implants. The n-well mask and p-well mask are used.
The gate material is formed over the diffusion region by depositing a polysilicon layer followed by a directional etch. Spacers are put on the edge of the fabricated devices using oxide or nitride layers. The source and drain diffusions are then created, typically by implanting boron and antimony (for p++ device regions) or arsenic and phosphorous (for n++ device regions).
A diode is an important circuit element. In a forward bias mode, a p-n diode conducts current after the forward diode voltage is exceeded according to the equation: EQU I=I.sub.sat (e.sup.qV/kT -1)
In the reverse bias mode, low level saturation leakage current flows until the breakdown voltage is exceeded. Avalanche breakdown voltage is the voltage where avalanche multiplication in the p-n diode depletion region is significant. At very high dopings, Zener breakdown occurs prior to avalanche breakdown. Both avalanche and Zener breakdown are non-destructive and allow for significant current to flow in the reverse biased configuration when these voltages are achieved.
A Zener or avalanche diode can have multiple applications. A Zener or avalanche diode can be fabricated so that it can be used to protect valuable or sensitive circuitry in IC semiconductors. These protective diodes can be integrated into an IC CMOS process with electronic circuitry or as independent semiconductor devices.
Zener diodes and avalanche diodes can also be used for on-chip electrostatic discharge protection (ESD) applications as independent diode elements or part of ESD devices or circuits. ESD networks can use Zener breakdown or avalanche breakdown to trigger the ESD network in overvoltage conditions.
ESD can be caused by charge build-up that can occur at several different stages of the integrated circuit fabrication process. For example, charge can be accumulated and discharged from module packaging machines, workers handling the packaged devices and contacting the circuit package input-output pins, etc. In addition, during exposure to plasma processing during the fabrication process, the polysilicon materials in the integrated circuit can accumulate an electrical charge that can cause damage to the gates of the integrated circuits. To prevent inadvertent circuit failure due to ESD, Zener diodes are placed into the circuit where they can act as buffers. When using Zener diodes to protect a circuit, the breakdown voltage of a diode must be low enough to ensure that either avalanche multiplication breakdown or Zener breakdown occurs prior to dielectric overvoltage or MOSFET secondary breakdown in the component circuitry.
As gate dielectric gets thinner, the use of standard n+ implants and wells as overvoltage "floating gate" tie downs becomes less useful due to the high breakdown voltage of the n+ implants and well implants. A typical diffusion breakdown exceeds 10 V while the gate dielectric breakdown voltage is decreasing well below this level in highly scaled VLSI CMOS devices. Hence, low breakdown voltage elements will be required.
Most integrated circuits are packaged with pins which are connected to input-output pads, thereby providing connections to the outside world. In a typical environment, the avalanche or Zener diode will be fabricated so as to protect the circuit connected to the input-output pads to an ESD human body model (HBM) specification of 2,000 v-4,000 v.
In a typical CMOS process, an avalanche or Zener diode is created when an n diffusion and p diffusion are abutted by implanting them next to each other. In some cases, the diffusions are slightly overlapped and in other cases a gate structure is included. Abutted junctions created in this fashion are typically unreliable and have variable leakage characteristics from junction to junction due to poor process control. This creates a diode that "leaks". However, as integrated circuit processing techniques have become more sophisticated, and as devices were increasingly scaled, the resistivity of the diffusions weren't keeping pace, so silicide processes were adopted to reduce the resistivity of the n diffusions and p diffusions. Silicides are typically created by placing a layer of refractory material such as titanium or cobalt over the surface of the wafer and then heating the wafer at a temperature range of 600.degree. C.-700.degree. C. Heating the wafer causes the silicon or polysilicon to react with the refractory materials to form suicides. The unreacted titanium on the oxide portions of the wafer is removed. The net result of the process is a low resistivity titanium suicide region wherever there is polysilicon and an n-diffusion or a p-diffusion. The silicide process, however, shunts or bridges the typical Zener diode and removes it from the circuit. Hence, with the silicide process shunting the abutted diode structure, no diode occurs.
It is becoming increasingly difficult to effectively create Zener diodes in certain integrated circuit processes. As explained above, device scaling is becoming an integral part of semiconductor design and fabrication processing. However, as scaling takes place, the gate oxide of the integrated circuit devices has become substantially thinner than the gate oxide used in earlier processes. Because of this, the breakdown voltage of the Zener diode may exceed the breakdown voltage of the gate oxide of a given integrated circuit device. If this happens, then the Zener diode is no longer capable of protecting the integrated circuit device and the device will suffer breakdown and fail before the Zener diode fails.
Given the increased demand for integrated circuits with ever smaller surface area, buried diodes are more desirable because they don't require any additional surface area. However, although buried Zener diodes can be fabricated using conventional methods, the current technology requires the use of at least four mask steps. This is time-consuming and significantly increases production costs. In addition, the alignment problems associated with using four masks severely restricts the possible size reductions of a typical Zener diode, making controlled fabrication of suitable Zener diodes at the sub-micron scale difficult, if not impossible.
In summary, although Zener diodes can be fabricated on the surface of a wafer, this process is not desirable because the Zener diode will consume valuable surface area, thereby restricting the reductions in the overall size of the circuit. Further, although buried Zener diodes can be fabricated using current technology, they cannot be made small enough for new, sub-micron sized circuit components.
Therefore, there exists a need to provide an improved method of creating buried Zener diodes with breakdown voltage levels which are low enough to protect integrated circuit components and gates from premature breakdown and ESD. Without additional methods for successfully creating more effective protective circuits and preparing new devices in integrated circuit manufacturing, additional design improvements, enhanced circuit performance, improved yield, and improved operational characteristics may be difficult to obtain.